aboutsummaryrefslogtreecommitdiff
path: root/sys/gen.py
diff options
context:
space:
mode:
Diffstat (limited to 'sys/gen.py')
-rwxr-xr-xsys/gen.py10
1 files changed, 6 insertions, 4 deletions
diff --git a/sys/gen.py b/sys/gen.py
index e1e8c0f..02ff952 100755
--- a/sys/gen.py
+++ b/sys/gen.py
@@ -103,9 +103,9 @@ def fmterrno(writer, musl):
continue
try:
if word[2].isdigit():
- putdefine(writer, errwrap(word[1]), word[2], left=30, right=30)
+ putdefine(writer, errwrap(word[1]), word[2], left=30, right=0)
else:
- putdefine(writer, errwrap(word[1]), errwrap(word[2]), left=30, right=30)
+ putdefine(writer, errwrap(word[1]), errwrap(word[2]), left=30, right=0)
except:
raise KeyError(f"{word[1]} not recognized")
@@ -232,7 +232,7 @@ def fmtsysnum(reader, writer):
sysn = word[2]
head = syscall(call)
if sysn.isdigit():
- print(f"#define {head:<30} {sysn:>30}", file=writer)
+ print(f"#define {head:<30} {sysn}", file=writer)
def fmtsysasm(reader, writer):
putline(writer)
@@ -301,6 +301,7 @@ int16 = "short"
int32 = "int"
int64 = {'x86_64':"long",'i386':"long long",'arm':"long long",'aarch64':"long",'riscv64':"long"}
addr = {'x86_64':"long",'i386':"int",'arm':"int",'aarch64':"long",'riscv64':"long"}
+reg = {'x86_64':"long",'i386':"int",'arm':"int",'aarch64':"long",'riscv64':"long"}
long64="0x7fffffffffffffffL"
long32="0x7fffffffL"
@@ -325,6 +326,7 @@ def fmtbits(writer, musl, arch):
putdefine(writer, "INT32", int32)
putdefine(writer, "INT64", int64[arch])
putdefine(writer, "ADDR", addr[arch])
+ putdefine(writer, "REG", reg[arch])
putline(writer)
putcomment(writer, "abi")
@@ -360,7 +362,7 @@ def putline(writer):
def putcomment(writer, string):
print(f"/* {string} */", file=writer)
-def putdefine(writer, name, value, left=20, right=00):
+def putdefine(writer, name, value, left=20, right=0):
print(f"#define {name:<{left}} {value:<{right}}", file=writer)
muslroot = "../vendor/musl"